Let’s change the world together!
USC is a leading private research university located in Los Angeles – a global center for arts, technology and international business. As the city’s largest private employer, responsible for more than $8 billion annually in economic activity in the region, we offer the opportunity to work in a dynamic and diverse environment, in careers that span a broad spectrum of talents and skills across a variety of academic schools and units. As a USC employee, you will enjoy excellent benefits and perks, and you will be a member of the Trojan Family - the faculty, staff, students and alumni who make USC a great place to work. Think you’ve got what it takes to join us? We invite you to search our open positions and apply!
Computer Scientist - ASIC Digital DesignApply Viterbi School of Engineering Arlington, Virginia
USC’s Information Sciences Institute (ISI), a unit of the university’s Viterbi School of Engineering, is a world leader in the research and development of advanced artificial intelligence, information processing, computing, and communications technologies. ISI’s 400 faculty, professional staff and graduate students carry out extraordinary information sciences research at three distinct locations - Marina Del Rey, CA; Arlington, VA; and Waltham, MA.
*This position is based in Arlington, VA. Remote work options are available *
The Reconfigurable Computing Group (RCG) at ISI is a leader in disrupting and advancing the fields of front-end ASIC and FPGA design, computer architecture, and EDA tools. As an applied research lab, our work spans the creation and maturation of ideas from academic conception to applied research prototypes.
RCG staff can be found:
- Researching and developing toolsets to map AI algorithms directly to hardware,
- Optimizing full scale testing of billion transistor FPGAs to minimal runtime,
- Performing experiments on the International Space Station,
- Utilizing ISI’s MOSIS service to fabricate novel computer architectures.
Our success is based on investing in our staff through a culture centered on:
- Learning and idea generation,
- Transparent and constructive feedback, and
- Continual growth through contributing to, creating, and leading a research agenda.
We are looking for highly talented, motivated researchers to lead research and development in the area of secure hardware. This position will collaborate with a high caliber team to create the world’s first customized accelerator for native Fully Homomorphic Encryption (FHE). Utilize custom EDA tools to synthesize, analyze, floorplan, and perform design space exploration of architectures over performance parameters. Be an active member of fast-paced ASIC Development team supporting the full life cycle from functional architecture definition to physical implementation, verification, and tape-out. Support efforts analyzing and evaluating the effectiveness of hardware security techniques such as obfuscation, logic locking, or programmability for use in advanced lithography nodes and real-world System on a Chip use cases in terms of quantifiable security, overhead, and useability metrics. This position will lead research, propose major innovations, collaborate with peers within the group and across ISI, publish results in top tier conferences, and contribute to or lead proposals.
Position specific JOB QUALIFICATIONS:
- PhD or MS and equivalent experience in Computer Engineering, Electrical Engineering, or Computer Science required.
- Established publication record in computer architecture, ASIC design, Fully Homomorphic Encryption hardware, or hardware security.
- 3-5 years of experience in Digital Design targeting 22nm or smaller lithography nodes.
- Expert level programming in Synthesizable C, VHDL, or Verilog.
- Experience interfacing and floor planning with bus (PCIe gen 4/5) memory (DDR3/4), and Single/Differential-ended I/O’s in System on Chip designs.
- Expert level user of standard digital design tools such as Cadence Stratus, Genus, and Innovus or Synopsys Synphony, Design Compiler, and IC compiler.
Preferred Job Qualifications:
- Experience targeting 12nm or smaller fabrication nodes a significant plus.
- Experience with clock tree insertion, scan-chain insertion, and back end layout a plus.
- Experience with Cadence JasperGold or Synopsys Formality a plus.
- Ability to handle export-controlled data. Per U.S. government regulations, eligibility to handle export-controlled data requires U.S. Citizenship or U.S. Permanent Residency.
The University of Southern California values diversity and is committed to equal opportunity in employment.
Minimum Education: Master's degree, Combined experience/education as substitute for minimum education Minimum Experience: 3 years Minimum Field of Expertise: Knowledge of research processes and computer science.
REQ20094041 Posted Date: 06/03/2021 Apply