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ApplyInformation Sciences InstituteArlington, Virginia
Information Sciences Institute (ISI), a unit of USC’s Viterbi School of Engineering, is a world leader in the research and development of advanced information processing, computing, and communications technologies. USC operates one of the world’s largest academic high-performance computing clusters. ISI has three research campuses: one in Marina del Rey, CA, one in Arlington, VA, and one in Waltham, MA.
*This position is located in Arlington, VA*
Information Sciences Institute (ISI) is looking for highly talented, motivated researchers to lead and impact state-of-the-art research and development in the area of reconfigurable computing. The Reconfigurable Computing Group (RCG) is a pioneer of research related to field programmable gate arrays (FPGAs) including architecture, tools, applications, hardware trust, and security. It works closely with leading agencies such as DARPA, IARPA, and NASA where reconfigurable computing is a critical technology. Spanning the days of homogeneous logic devices to today’s billion transistor system on a chip devices, RCG has led the way from being the first to implement application-level partial runtime reconfiguration, investigating 3D FPGA architectures, developing autonomous system on chip architectures, releasing open source CAD tools that target real physical devices, and IP to address software/hardware co-design complexity. Today, RCG is addressing our nation’s challenges in big data, hardware cybersecurity, trusted systems, cognitive radio and more.
This position will lead the research and technical direction of RCG’s thrust in Abstractions for Reconfigurable Computing, which enable traditional software developers to develop FPGA and ASIC designs and increase the productivity of hardware designers. Architect and lead the development of complex platform tools which support highly specialized domains. Perform research on ground breaking CAD solutions, including integration with higher level hardware/software co-design and HLS solutions, and deployment in Amazon AWS F-1. Realize effectiveness of solutions on physical FPGAs and custom ASIC fabrication. Lead research, propose major innovations, collaborate with peers within the group and across ISI, publish results in top tier conferences, and contribute to or lead proposals.
Required Job Qualifications
Qualified candidates for this position must be willing and eligible to apply for a collateral Secret clearance. Eligibility for this clearance requires U.S. citizenship. Current SECRET clearance or higher is a plus.
PhD or equivalent experience in Electrical Engineering, Computer Engineering, or Computer Science with experience in Verilog/VHDL/C programming for FPGAs.
Five years of strong Python/C++ development experience, including demonstrable contributions to large-scale Python/C++ projects. Commercial or open-source development experience a plus.
Five years of experience designing, developing, implementing, and debugging firmware for FPGAs, including Xilinx Virtex7 or later architectures. Experience with Intel Aria-10 and Stratix-10 devices also desirable.
Experience with multi-processor system-on-chip, embedded systems software (Linux, cross-compilers) and Python productivity for FPGAs (i.e. Pynq).
Detailed understanding of mapped and unmapped netlist formats, such as EDIF, XDL, and structural Verilog.
Proficiency in hardware development in VHDL or Verilog, or SystemC or SystemVerilog.
Previous publications, patents, or innovations related to FPGA productivity, CAD or EDA algorithms and tools.
Preferred Job Qualifications
Experience with Amazon EC2 F1 instances or related FPGA-based cloud platforms.
Experience with Torc, ABC, VPR, VTR, RapidSmith, GoAhead, or similar commercial tools a plus.
Experience in device level reliability, fault tolerance, or security a plus.
Experience leading or contributing to proposals a significant plus.
The University of Southern California values diversity and is committed to equal opportunity in employment.