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USC is a leading private research university located in Los Angeles – a global center for arts, technology and international business. As the city’s largest private employer, responsible for more than $8 billion annually in economic activity in the region, we offer the opportunity to work in a dynamic and diverse environment, in careers that span a broad spectrum of talents and skills across a variety of academic schools and units. As a USC employee, you will enjoy excellent benefits and perks, and you will be a member of the Trojan Family - the faculty, staff, students and alumni who make USC a great place to work. Think you’ve got what it takes to join us? We invite you to search our open positions and apply!

Senior Computer/Electronics Engineer - ASIC Digital Design

Viterbi School of Engineering Arlington, Virginia

USC’s Information Sciences Institute (ISI), a unit of the university’s Viterbi School of Engineering, is a world leader in the research and development of advanced artificial intelligence, information processing, computing, and communications technologies. ISI’s 400 faculty, professional staff and graduate students carry out extraordinary information sciences research at three distinct locations - Marina Del Rey, CA; Arlington, VA; and Waltham, MA.

*This position is based in Arlington, VA. Remote work options are available *

The Reconfigurable Computing Group (RCG) at ISI is a leader in disrupting and advancing the fields of front-end ASIC and FPGA design, computer architecture, and EDA tools. As an applied research lab, our work spans the creation and maturation of ideas from academic conception to applied research prototypes.

RCG staff can be found:

  • Researching and developing toolsets to map AI algorithms directly to hardware,
  • Optimizing full scale testing of billion transistor FPGAs to minimal runtime,
  • Performing experiments on the International Space Station,
  • Utilizing ISI’s MOSIS service to fabricate novel computer architectures.

Our success is based on investing in our staff through a culture centered on:

  • Learning and idea generation,
  • Transparent and constructive feedback, and
  • Continual growth through contributing to, creating, and leading a research agenda.

We are looking for highly talented, motivated researchers to lead research and development in the area of secure hardware. Be a member of a high caliber team creating the world’s first customized accelerator for native Fully Homomorphic Encryption (FHE). Lead the synthesis and floorplanning of complex FHE architectures utilizing custom EDA tools. Be an active member of fast-paced ASIC Development team supporting the full life cycle from functional architecture definition to physical implementation, verification, and tape-out. Support efforts analyzing and evaluating the effectiveness of hardware security techniques such as obfuscation, logic locking, or programmability for use in advanced lithography nodes and real-world System on a Chip use cases in terms of quantifiable security, overhead, and useability metrics. Lead development while contributing to advanced research, collaborating with peers within the group and across ISI, and contributing to publications in top tier conferences.

Position specific JOB QUALIFICATIONS:

  • Graduate degree or equivalent experience in Computer Engineering, Electrical Engineering, or Computer Science required.
  • 5-10 years of experience in Digital Design targeting and fabricating 22nm or smaller lithography nodes.
  • Expert level programming in Synthesizable C, VHDL, or Verilog.
  • Experience interfacing and floorplanning with bus (PCIe gen 4/5), memory (DDR3/4), and Single/Differential-ended I/O’s in System on Chip designs.
  • Expert level user of standard digital design tools such as Cadence Stratus, Genus, and Innovus or Synopsys Synphony, Design Compiler, and IC compiler.
  • Previous experience with PCB design.

Preferred Job Qualifications:

  • Experience targeting 12nm or smaller fabrication nodes a significant plus
  • Experience with clock tree insertion, scan-chain insertion, and back end layout a plus.
  • Experience with Cadence JasperGold or Synopsys Formality a plus.
  • Experience with software revision control systems such as Git, Mercurial, SVN, etc
  • Ability to handle export-controlled data. Per U.S. government regulations, eligibility to handle export-controlled data requires U.S. Citizenship or U.S. Permanent Residency.

The University of Southern California values diversity and is committed to equal opportunity in employment.

Minimum Education: Master's degree, Combined experience/education as substitute for minimum education Minimum Experience: 3 years Minimum Field of Expertise: Working knowledge of electrical & computer engineering; experience with CAE/CAD tools, modern design methodologies & development of solutions for specific design tasks using engineering principles.

REQ20098453 Posted Date: 09/13/2021

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