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VLSI Design & Development ScientistApply Information Sciences Institute Arlington, Virginia
USC’s Information Sciences Institute (ISI), a unit of the university’s Viterbi School of Engineering, is a world leader in the research and development of advanced artificial intelligence, information processing, computing, cybersecurity, and communications technologies. ISI’s 400 faculty, professional staff and graduate students carry out extraordinary information sciences research at three distinct locations - Marina Del Rey, CA; Arlington, VA; and Waltham, MA.
*This position is located in Arlington, VA.*
The Application Specific Intelligent Computing (ASIC) Research Lab is seeking a VLSI design and development scientist with experience in (1) design and simulation of SRAM (single port or multi-port), (2) with knowledge of ASIC/custom design flow, Stating Timing Analysis and Parasitic Extraction, (3) comprehensive understanding of methodologies of timing closure, design-for-test, signal integrity closure, DFM closure, physical verification, deep sub-micron issues (4) Experience in various timing (STA), DFT, Noise, P&R, DRC/VLS (5) working experience with semiconductor foundries. The research will include work on 22 nm FDSOI or 12 nm FINFET technology nodes (6) physical characterization and debugging of fabricated chips. The candidate will work with internal and external research and foundry partners to prototype novel homomorphic encryption integrated chip solutions.
• Ph.D. Electrical Engineering, or related field with experience in design, fabrication, and/or characterization of VLSI circuits
• Knowledge of SRAM and understanding of non-volatile memory technologies
• Experience with design and circuit simulation tools such as cadence or synopsis.
• Must have experience in scripting, Verilog HDL, design compilers, formal verification tools, design for test, Automatic test pattern generation, place and route tool, clock insertion, Static timing analysis tools, Schematics and layout editors, physical design verification, parasitic extraction tools based on Synopsis or Cadence or Mentor graphics.
• Experience in tapeout of the designs in advanced technology foundries.
• Knowledge of electrical characterization techniques and advanced packaging techniques is desirable.
• Candidate must have excellent written and verbal communication skills and be able to work independently and in a dynamic multi-disciplinary team environment.
• Strong interpersonal skills, organizational skills, program management experience, and ability to multitask.
• Demonstrated ability to meet business deadlines.
• Experience in benchmarking and articulate the value proposition of the photonics integrated circuit.
• Experience with technology transfer to the industry.
The University of Southern California values diversity and is committed to equal opportunity in employment.
Minimum Education: Master's degree, Combined experience/education as substitute for minimum education Minimum Experience: 5 years Minimum Field of Expertise: Thorough knowledge of VLSI electrical and computer engineering principles at the chip level; experience with CAE/CAD tools, modern design methodologies and development of solutions for specific design tasks using VLSI engineering principles.
REQ20093587 Posted Date: 09/29/2020 Apply